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Research PaperResearchia:202607.21083

Fixed Point Exploration For CV-QKD IR QC-MET-LDPC Toward Hardware Implementation

Guilherme Vergne de Oliveira

Abstract

High-speed LDPC decoding is a major bottleneck in CV-QKD and motivates hardware acceleration with fixed-point arithmetic. This work compares SPA, MSA, and NMS under a unified low-SNR fixed-point framework using common graph, matrix, and quantization settings. Multiple formats are evaluated through FER, and average iterations. The results show that performance depends strongly on the interaction between decoder rule and numerical precision. SPA achieved the best overall performance. For reduced-c...

Submitted: July 21, 2026Subjects: Quantum Physics; Quantum Computing

Description / Details

High-speed LDPC decoding is a major bottleneck in CV-QKD and motivates hardware acceleration with fixed-point arithmetic. This work compares SPA, MSA, and NMS under a unified low-SNR fixed-point framework using common graph, matrix, and quantization settings. Multiple formats are evaluated through FER, and average iterations. The results show that performance depends strongly on the interaction between decoder rule and numerical precision. SPA achieved the best overall performance. For reduced-complexity decoders, Q16.8 was the lowest consistent precision, with NMS outperforming MSA. Practically, SPA with Q8.4 offered the best balance between reliability and hardware efficiency for large-scale implementations.


Source: arXiv:2607.17960v1 - http://arxiv.org/abs/2607.17960v1 PDF: https://arxiv.org/pdf/2607.17960v1 Original Link: http://arxiv.org/abs/2607.17960v1

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Date:
Jul 21, 2026
Topic:
Quantum Computing
Area:
Quantum Physics
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